1. Field of the Invention
This invention relates to an electro-optical device such as a liquid crystal display device, and particularly to a display device having an active matrix circuit.
2. Description of Prior Art
Recently, an active matrix circuit for driving a liquid crystal display has been actively studied and put into practical use. As an active element has been proposed one having a construction that a conductive-type thin film transistor (TFT) is used for a picture element. Such an active matrix circuit has capacitors each comprising a picture-element electrode, a counter electrode and liquid crystal interposed between these electrodes, and charges to be supplied to and discharged from the capacitor are controlled by a TFT. In order to perform a stable image display, a voltage across both electrodes of each capacitor is required to be kept constant, however, it has been difficult to satisfy this requirement for some reasons.
The most significant reason is that charges leak from the capacitor even when the TFT is in an off-state. There is another leakage of charges inside of the capacitor, however, the former leakage of the charges from the TFT is larger than the latter leakage by about one order. When this leakage occurs intensively, there occurs a phenomenon, so-called flicker that light and darkness of an image is varied at the same frequency as a frame frequency. As another reason, a gate signal is capacitively coupled to a picture-element potential due to parasitic capacitance between a gate electrode of the TFT and the picture-element electrode to induce variation of a voltage (ΔV).
In order to solve these problems, an auxiliary (or additive) capacitance has been disposed in parallel to the picture-element capacitance. Provision of such an auxiliary capacitance causes a time constant of discharging of charges from the picture-element capacitance to be increased. In addition, representing a gate pulse (signal voltage) by VG, the picture-element capacitance by CLC, the auxiliary capacitance by C, and the parasitic capacitance between the gate electrode and the picture-element electrode by C′, ΔV is represented as follows;ΔV=C′VG/(CLC+C′+C)and ΔV can be reduced if C is larger than C′ and CLC.
Conventionally, a circuit construction as shown in FIG. 2(A) or 2(B) has been adopted for the auxiliary capacitance. These circuit arrangements are shown by circuit diagrams of FIGS. 2(C) and 2(D), respectively. In the circuit arrangement as shown in FIG. 2(B), a ground line, for example Xn′ is formed in parallel to a gate line Xn (or data line Ym), and a picture-element electrode is formed so as to be overlapped with the ground line, thereby forming a capacitance C. In FIG. 2(B), the auxiliary capacitance C is represented by an oblique-line portion, and CLC represents a picture-element electrode. However, in this circuit arrangement (method), a wiring is required to be newly formed, and thus there is a disadvantage that the aperture ratio is reduced and a screen is darkened.
On the other hand, in the circuit arrangement as shown in FIG. 2(A), a picture-element electrode which is connected to the gate line Xn is partially overlapped with a next gate line Xn+1 to form an auxiliary capacitance C (as indicated by an oblique-line portion) at the overlap portion. In this case, no wiring is required to be newly formed, and thus the aperture ratio is not reduced. However, it has been known that a gate pulse is affected by capacitance which is added to the gate line.
At any rate, in these methods (circuit arrangements), substantially no solution have been made particularly to ΔV. These methods provide some degree of effect in a point that the time constant of the discharging of the picture element is lengthened, however, no solution has been made to the point that ΔV occurs asymmetrically. FIG. 3(C) shows a driving operation of a conventional TFT active matrix circuit. In this case, the potential of a counter electrode of a picture-element electrode is set to “0” V, and the potential of the gate line at non-selection time is also set to “0” V. However, as usually adopted, the potential of the counter electrode may be added with a proper offset potential while the potential of the data line is also added with the same offset potential. Actually, the same result as shown in FIG. 3 is obtained. Particularly when the potential of the gate line and the potential of the counter electrode are set to zero as shown in FIG. 3, the signal of the data line is required not to exceed a threshold voltage of the TFT, and no stable matrix driving can be performed unless this condition is satisfied.
As is apparent from FIG. 3, ΔV is shifted with respect to the data signal in such a direction that the potential thereof is decreased. For example, even when an auxiliary capacitance is added to reduce ΔV, the response is still asymmetrical. In this point, the provision of the auxiliary capacitance is a negative countermeasure.